Overview Rambus, a premier chip, and silicon IP provider, is seeking to hire an exceptional mid-level Design and Verification Engineer to join our PHY integration team in Sofia, Bulgaria. The successful candidate will participate in pre-silicon RTL
Rambus is hiring a full-time Senior Design engineer for the PCIe/CXL IP design team in a hybrid setup with onsite and remote work. The role focuses on architecture, micro-architecture, and implementation in SystemVerilog, with FPGA prototyping and
A premier silicon technology firm is seeking a mid-level Design and Verification Engineer. The role involves Verilog RTL design and verification for PCIe Controller development. Candidates should have 6+ years of experience in verification, strong analytical
Overview Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full‑time Senior Design engineer to join our PCIe, CXL IP design team. Candidates will be joining some of the brightest inventors and