Company Description Mixel, a Silvaco Company, is an innovator of high-performance analog mixed signal semiconductor IPs whose solutions are powering Mobile, Display, Camera, Automotive, VR, AR and AI applications. Our mission is to provide our customers
The Role: As an AI Kernel optimization Engineer, you will play a key role in pushing the limits of AI inference performance on Openchip RISC-V platforms. You will design, implement, and optimize AI compute kernels (Gen
Snap Inc is a technology company. We believe the camera presents the greatest opportunity to improve the way people live and communicate. Snap contributes to human progress by empowering people to express themselves, live in the
About Pinterest: Millions of people around the world come to our platform to find creative ideas, dream about new possibilities and plan for memories that will last a lifetime. At Pinterest, we’re on a mission to bring
Company:Qualcomm France S.A.R.L. Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: QUALCOMM is a global leader in smart mobile technologies, providing comprehensive solutions that drive continuous innovation for todays connected devices. By pushing the boundaries
Company:Qualcomm France S.A.R.L. Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: The QITC mission is to develop and deploy custom-built interconnect hardware IPs, software tools, and exploration and verification methodologies so that SoC integration teams
About Us Harmattan AI is a next-generation defense prime building autonomous and scalable defense systems. Following the close of a $200M Series B, valuing the company at $1.4 billion, we are expanding our teams and capabilities
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. ATE Test Engineer Junior Position Summary We are looking for a motivated ATE Test Engineer to
Company:Qualcomm France S.A.R.L. Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: The QITC mission is to develop and deploy custom-built interconnect hardware IPs, software tools, and exploration and verification methodologies so that SoC integration teams
Work ScheduleStandard (Mon-Fri) Environmental ConditionsOffice Job Description Thermo Fisher Scientific Language Services is expanding its Language Specialist team to support biotech, medical device, and product-focused clients. We are seeking an experienced French Language Specialist with a
A growing, innovator in the semiconductor system IP domain is searching for a key contributor to define and optimize cache coherency solutions. You will be a leading figure in developing cutting‑edge cache‑coherent interconnect IP and ensuring
Entity presentation The position is offered in the ASiC team of the Digital Plant - Modicon line of business, in the Industry Business Unit of Schneider Electric. The ASiC team has the following missions: Define the
Looking for someone to join us as an early member of the AI Operations team, the group dedicated to integrating AI across all levels of the company. In the initial months, youll be working closely with
Responsibilities Serve as the technical authority for pixel reconstruction algorithms, influencing imaging architecture decisions across ISP, sensor, optics, and AI imaging pipelines, and driving improvements in end-user perceptual video quality and overall camera experience. Collaborate closely
The Opportunity Lumai is redefining how the world computes. We are an ambitious, venture-backed UK startup pioneering a breakthrough AI accelerator for data centers which uses 3D optical compute. Our radical technology uses light to perform
Looking for someone to join us as an early member of the AI Operations team, the group dedicated to integrating AI across all levels of the company. In the initial months, youll be working closely with
Overview Arteris is seeking a Cache Coherency Architect to define and optimize cache coherency solutions within Arteris advanced NoC IP portfolio. You will collaborate with hardware designers, verification engineers, software developers, and other stakeholders to create
For our Business Line Secure Transactions & Interfaces (STI) in France, we are now looking for a Digital FPGA Platform Leader. This role is part of the System on Chips (SoC’s) Design & Integration Team within
The role As Senior AI Kernel Optimization Engineer, you will lead the optimization of high-performance kernels to push the limits of AI Inference on Openchip RISC-V platforms. You will design, implement, and optimize AI compute kernels
About Us Axelera AI is not your regular deep-tech startup. We are creating the next‑generation AI platform to support anyone who wants to help advancing humanity and improve the world around us. In just four years,