About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world.
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world.
SiFive is seeking a hardware design engineer in La Ciotat, France, with extensive experience in designing advanced debug, trace, and profiling hardware for RISC-V architectures. The role involves collaborating with multiple teams to bring new hardware
Job Description SiFive is seeking a hardware design engineer passionate about designing industry‑leading debug, trace and profiling IP to support the widespread adoption of RISC‑V as the architecture of choice for SOC designs. The engineer will
Job Responsibilities Architect, design and implement debug, trace and profiling hardware. Work with architecture, performance, software and hardware teams in architecture/microarchitecture exploration and specification. Implement RTL generators such that elements self‑configure to optimally design‑in extensive configurability
Job Description SiFive is seeking a hardware design engineer who is passionate about designing industry‑leading debug, trace and profiling IP to help drive the tidal wave of adoption of RISC‑V as the architecture of choice for
# Debug/Trace/Profiling Design EngineerApplylocations: La Ciotat, France: Cambridge, England, United Kingdom: Austin, Texas, United States: Boston, Massachusetts, United Statestime type: Full timeposted on: Posted 6 Days Agojob requisition id: R- # About SiFive *As the pioneers